NXP Semiconductors /MIMXRT1064 /IOMUXC /SW_MUX_CTL_PAD_GPIO_B1_15

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SW_MUX_CTL_PAD_GPIO_B1_15

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALT0)MUX_MODE 0 (DISABLED)SION

SION=DISABLED, MUX_MODE=ALT0

Description

SW_MUX_CTL_PAD_GPIO_B1_15 SW MUX Control Register

Fields

MUX_MODE

MUX Mode Select Field.

0 (ALT0): Select mux mode: ALT0 mux port: ENET_MDIO of instance: enet

1 (ALT1): Select mux mode: ALT1 mux port: FLEXPWM4_PWMA03 of instance: flexpwm4

2 (ALT2): Select mux mode: ALT2 mux port: CSI_MCLK of instance: csi

3 (ALT3): Select mux mode: ALT3 mux port: XBAR1_IN03 of instance: xbar1

4 (ALT4): Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO31 of instance: flexio2

5 (ALT5): Select mux mode: ALT5 mux port: GPIO2_IO31 of instance: gpio2

6 (ALT6): Select mux mode: ALT6 mux port: USDHC1_RESET_B of instance: usdhc1

8 (ALT8): Select mux mode: ALT8 mux port: ENET2_TDATA01 of instance: enet2

9 (ALT9): Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO31 of instance: flexio3

SION

Software Input On Field.

0 (DISABLED): Input Path is determined by functionality

1 (ENABLED): Force input path of pad GPIO_B1_15

Links

() ()